Various metal silicides, such as cobalt silicide, are used in the art as contact materials for forming contacts to silicon in CMOS devices. The use of metal silicides is desirable due to the low resistivity, high stability, and small lattice mismatch with silicon that is achievable with these materials. Moreover, as compared to many other contact materials, metal silicides can be readily patterned into relatively small dimensions.
Unfortunately, the ongoing trend toward smaller device sizes in semiconductor fabrication processes is currently testing the limitations of silicide technology. In particular, as polysilicon gate lengths decrease, it becomes increasingly challenging to form uniform layers of silicide on these gates. Indeed, at dimensions below about 50 nm, extensive voiding and silicide spiking can occur during silicide formation. Consequently, at these dimensions, uniform silicide films cannot be formed in a reproducible manner using current technologies.
Some attempts have been made in the art to overcome this problem. For example, in some applications, overetching of spacer structures has been employed to expose additional surface area on the gate. This technique permits the formation of more uniform silicide films on gate structures of smaller gate lengths, since it increases the total surface area available for the formation of the silicide film. However, the reductions in gate lengths achievable with this technique have been found to be incremental at best, since the electrical properties of the resulting structures are found to degrade rapidly as the extent of overetching increases.
There is thus a need in the art for a method for forming silicided polysilicon gates in semiconductor devices which overcomes the aforementioned infirmity. In particular, there is a need in the art for a method for reproducibly forming silicided polysilicon gates in which the gates have reduced dimensions, without adversely affecting the electrical properties of the semiconductor device. These and other needs may be met by the devices and methodologies described herein.